The present invention relates to a method for establishing a distribution of I/O circuits in an application-specific integrated circuit (ASIC), and more particularly to a method for insuring that a distribution of I/O circuits complies with voltage drop (IR) and electro-migration (EM) requirements for the ASIC.
In an ASIC, a power grid comprising a plurality of power buses supplies current to logic circuitry and I/O circuits used to drive signals on and off a chip housing the ASIC. In determining a distribution of the I/O circuits, IR (current x resistance) drops and EM limits on the chip design must be taken into consideration. For example, if I/O circuits are clustered too densely within a given area, IR and EM limits of the chip may be exceeded, causing a logic or electrical failure.
Power buses that supply power to I/O circuits also provide power to the logic circuitry of the chip, and consequently, for best accuracy, currents of the logical circuitry should be included in an analysis of IR and EM behavior of the chip.
Existing methods of performing analysis of the distribution of I/O circuits in chip design have disadvantages. For example, power distribution analysis is typically performed late in the overall design process. Most existing approaches utilize an extraction process. The extraction process extracts shape data from the geometric pattern comprising the conducting lines in which current flows on a chip. The shape data is processed by extraction techniques to convert the shape data into a resistance matrix, which would then be solved. The extraction process is typically time-intensive and creates extremely large resistance models, which can take many hours or days to solve.
Moreover, existing methods tend to be overly localized. A designer may refer to guidelines, which recommend that circuits be placed in a certain density per unit area. However, such an approach fails to take into account the current requirements of the overall power distribution grid, and consequently can introduce inefficiencies in power distribution analysis. For example, guidelines that specify a maximum number of allowable I/O circuits within a specified area, but do not account for neighboring areas that maybe empty or occupied by low power circuits, thus demanding less current, typically force designers to adjust I/O circuits placement when a broader analysis may show that no placement changes are needed.
In view of the foregoing, a method for I/O circuit distribution analysis is needed which addresses the noted disadvantages of existing methods.